Neuromorphic processors for edge inference.
We design spiking neural network processors from scratch in Verilog and validate them on real FPGA hardware. Event-driven cores that fire only on input, learn on-chip through programmable plasticity rules, and run at a fraction of the power of conventional accelerators. Four generations designed. Two open sourced.
Independently developed, drawing on published neuromorphic concepts. 14-opcode microcode learning engine, barrier-synchronised mesh network-on-chip with multi-chip serial links, triple RV32IMF RISC-V cluster. Validated on AWS F2 (VU47P) and Kria K26.
Programmable microcode neurons, independently developed. Graded spike transmission, eligibility traces, reward-modulated plasticity. FPGA-validated on AWS F2. SDK with CPU, GPU, UART, and PCIe backends.
Time-division multiplexed virtualisation, async hybrid NoC with adaptive routing, multi-threaded on-chip learning, hardware short-term plasticity and homeostatic scaling.
FPGA-validated spiking classifier: the full SHD test set runs byte-identical on hardware, scaled to a 393,216-neuron fabric, with 32 networks resident and field-switchable, spikes passing between two FPGAs, driven by an on-chip RISC-V management core. The compute tile has completed clean physical signoff on a 130nm process; the full chip is in physical design (pre-fabrication).
N4's SHD 90.28% is measured on chip, bit-exact. The figures above are software benchmarks (trained on GPU, 16-bit quantized) on the FPGA-validated architectures.
Open to research collaboration, FPGA contract work, and partnerships.