Research
Four processor generations. Four open-access papers. FPGA validated on AWS F2 and Kria K26.
N4
Coming soonDeliver-mode spiking inference engine, validated bit-exact against a golden model on AWS F2 (VU47P) at 62.5 MHz. Scaled to 393,216 neurons on a single FPGA; SHD 90.28% measured on chip across the full test set. Edge variant on Kria K26 at 0.378 W total board power. 28 nm ASIC in design; 130 nm compute tile signed off.
N4-Edge
Low-power embedded variant. SRAM-only. Targets $5-20 FPGA modules.
Architecture evolution
Each generation extends the ISA and adds hardware capabilities. N1 through N3 have dedicated product pages with full specifications.
| N1 | N2 | N3 | N4 | |
|---|---|---|---|---|
| Cores | 128 | 128 | 128 (16 tiles) | 48 (FPGA) |
| Neurons | 131K | 131K | 524K–1M | 393,216 (FPGA) |
| Neuron models | 1 (CUBA LIF) | 5 | 7+ (programmable) | 3 (LIF, CUBA, adLIF) |
| Neuron engine | Fixed datapath | Microcode | Microcode + ANN mode | Deliver-mode, bit-exact |
| Weight precision | 8-bit fixed | 1–16-bit variable | 1–16-bit variable | 16-bit fixed |
| Spike formats | Binary | Binary + graded | Binary + graded + compressed | Binary + graded |
| Learning | STDP + reward | 3-factor + homeostatic | Per-tile | Readout adaptation (measured) |
| Synapse formats | 3 | 4 | 4 + compression | Weighted CSR |
| Memory | 1 level | 1 level | Multi-level | On-die SRAM + DDR model store |
| Virtualization | — | — | TDM | 32-context TDM |
| FPGA validated | VU47P (16-core) | VU47P | F2 + K26 | F2 + K26 |
| ASIC projection | — | 19–38 mW (28 nm) | — | 100–300 mW (28 nm) |
FPGA validation
All four generations validated on physical FPGA fabric. RTL on hardware at clock speed, compared bit-exact against a CPU reference simulator. Covers neuron dynamics, synaptic formats, mesh routing, on-chip learning, microcode execution, and state isolation.
Benchmarks
Standard neuromorphic benchmark suite. SHD, SSC, N-MNIST, DVS Gesture. Results reported alongside current state-of-the-art. The architecture is competitive on SHD (91.0% vs 96.4% SOTA). The gap is in training methodology, not hardware capability.
Publications
Catalyst N2: An Open Neuromorphic Processor with Programmable Neuron Microcode
Programmable neuron microcode, variable-precision weights, 3-factor learning with homeostatic plasticity, graded spike payloads.
DOI 10.5281/zenodo.18728256Catalyst N1: A 131K-Neuron Open Neuromorphic Processor with Programmable Synaptic Plasticity
128 cores, 131,072 CUBA LIF neurons, STDP + reward-modulated plasticity, 14-opcode learning ISA, SHD 90.6%.
DOI 10.5281/zenodo.18727094Software
The SDK includes three execution backends. The CPU backend is the reference implementation. Every commit is tested against all three.